HD6473837H Datasheet, PDF (528/562 Pages) Renesas Technology Corp – Hardware Manual

IRR2—Interrupt request register 2
H'F7
System control
Bit
Initial value
Read/Write
7
IRRDT
0
R/W *
6
IRRAD
0
R/W *
5
IRRS2
0
R/W *
4
3
2
IRRTG IRRTFH IRRTFL
0
0
0
R/W* R/W* R/W*
1
IRRTC
0
R/W *
0
IRRTB
0
R/W *
Timer B interrupt request flag
0 [Clearing condition] When IRRTB = 1, it is cleared by writing 0
1 [Setting condition] When the timer B counter overflows from
H'FF to H'00
Timer C interrupt request flag
0 [Clearing condition] When IRRTC = 1, it is cleared by writing 0
1 [Setting condition] When the timer C counter overflows from H'FF to H'00
or underflows from H'00 to H'FF
Timer FL interrupt request flag
0 [Clearing condition] When IRRTFL = 1, it is cleared by writing 0
1 [Setting condition] When counter FL matches output compare register FL
in 8-bit mode
Timer FH interrupt request flag
0 [Clearing condition] When IRRTFH = 1, it is cleared by writing 0
1 [Setting condition]
When counter FH matches output compare register FH in
8-bit mode, or when 16-bit counter F (TCFL, TCFH)
matches 16-bit output compare register F (OCRFL,
OCRFH) in 16-bit mode
Timer G interrupt request flag
0 [Clearing condition] When IRRTG = 1, it is cleared by writing 0
1 [Setting condition] When pin TMIG is set to TMIG input and the
designated signal edge is detected
SCI2 interrupt request flag
0 [Clearing condition] When IRRS2 = 1, it is cleared by writing 0
1 [Setting condition] When an SCI2 transfer is completed or aborted
A/D converter interrupt request flag
0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0
1 [Setting condition] When A/D conversion is completed and ADSF is reset
Direct transfer interrupt request flag
0 [Clearing condition] When IRRDT = 1, it is cleared by writing 0
1 [Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct
transfer is made
Note: * Only a write of 0 for flag clearing is possible.
511