HD6473837H Datasheet, PDF (219/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 6: CMFH
0
1
Description
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
Setting conditions:
Set when the TCFH value matches OCRFH value
(initial value)
Bit 5—Timer Overflow Interrupt Enable H (OVIEH): Bit 5 enables or disables TCFH
overflow interrupts.
Bit 5: OVIEH
0
1
Description
TCFH overflow interrupt disabled
TCFH overflow interrupt enabled
(initial value)
Bit 4—Counter Clear H (CCLRH): In 16-bit mode, bit 4 selects whether or not TCF is cleared
when a compare match occurs between TCF and OCRF.
In 8-bit mode, bit 4 selects whether or not TCFH is cleared when a compare match occurs between
TCFH and OCRFH.
Bit 4: CCLRH
0
1
Description
16-bit mode: TCF clearing by compare match disabled
8-bit mode: TCFH clearing by compare match disabled
16-bit mode: TCF clearing by compare match enabled
8-bit mode: TCFH clearing by compare match enabled
(initial value)
Bit 3—Timer Overflow Flag L (OVFL): Bit 3 is a status flag indicating TCFL overflow (H'FF
to H'00). This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 3: OVFL
0
1
Description
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting conditions:
Set when the value of TCFL goes from H'FF to H'00
(initial value)
Bit 2—Compare Match Flag L (CMFL): Bit 2 is a status flag indicating a compare match
between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set
by software.
202