HD6473837H Datasheet, PDF (278/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 0—Multiprocessor Bit Transmit (MPBT): Bit 0 holds the multiprocessor bit to be added to
transmitted data when a multiprocessor format is used in asynchronous mode. Bit MPBT is
ignored when synchronous mode is chosen, when the multiprocessor communication function is
disabled, or when data transmission is disabled.
Bit 0: MPBT
0
1
Description
The multiprocessor bit in transmit data is 0
The multiprocessor bit in transmit data is 1
(initial value)
Bit Rate Register (BRR)
Bit
Initial value
Read/Write
7
BRR7
1
R/W
6
BRR6
1
R/W
5
BRR5
1
R/W
4
BRR4
1
R/W
3
BRR3
1
R/W
2
BRR2
1
R/W
1
BRR1
1
R/W
0
BRR0
1
R/W
The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock
selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit
rate.
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Table 10.8 gives examples of how BRR is set in asynchronous mode. The values in
table 10.8 are for active (high-speed) mode.
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