HD6473837H Datasheet, PDF (121/562 Pages) Renesas Technology Corp – Hardware Manual

5.7 Active (medium-speed) Mode
5.7.1 Transition to Active (medium-speed) Mode
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ₀, IRQ₁, or WKP₀ to WKP₇ interrupts in standby
mode, timer A, IRQ₀, or WKP₀ to WKP₇ interrupts in watch mode, or any interrupt in sleep mode.
A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or
the particular interrupt is disabled in the interrupt enable register.
5.7.2 Clearing Active (medium-speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction or by a input at the RES pin.
Clearing by SLEEP Instruction: A transition to standby mode takes place if a SLEEP
instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is
cleared to 0, and TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY
bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1 when a SLEEP instruction is executed.
Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is
executed. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See
5.8, Direct Transfer, below for details.
Clearing by RES Pin: When the RES pin goes low, the CPU enters the reset state and active
(medium-speed) mode is cleared.
5.7.3 Operating Frequency in Active (medium-speed) Mode
In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed)
mode.
5.8 Direct Transfer
5.8.1 Direct Transfer Overview
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
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