HD6473837H Datasheet, PDF (218/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 2: CKSL2 Bit 1: CKSL1 Bit 0: CKSL0 Description
0
*
*
External event (TMIF). Rising or falling edge
is counted*¹
(initial value)
1
0
0
Internal clock: φ/32
1
Internal clock: φ/16
1
0
Internal clock: φ/4
1
Internal clock: φ/2
Note: 1. The edge of the external event signal is selected by bit IEG3 in the IRQ edge select
register (IEGR). See 3.3.2, for details on the IRQ edge select register. Note that
switching the TMIF pin function by changing bit IRQ3 in port mode register 1 (PMR1)
from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F
counter to be incremented.
* Don’t care
Timer Control/Status Register F (TCSRF)
Bit
7
6
5
OVFH CMFH OVIEH
Initial value
0
0
0
Read/Write R/W* R/W* R/W
Note: * Only 0 can be written, to clear flag.
4
CCLRH
0
R/W
3
OFL
0
R/W*
2
CMFL
0
R/W*
1
OVIEL
0
R/W
0
CCLRL
0
R/W
TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare
match indication, and enabling of interrupts caused by timer overflow.
Upon reset, TCSRF is initialized to H'00.
Bit 7—Timer overflow flag H (OVFH): Bit 7 is a status flag indicating TCFH overflow (H'FF to
H'00). This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: OVFH
0
1
Description
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting conditions:
Set when the value of TCFH goes from H'FF to H'00
(initial value)
Bit 6—Compare Match Flag H (CMFH): Bit 6 is a status flag indicating a compare match
between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set
by software.
201