HD6473837H Datasheet, PDF (262/562 Pages) Renesas Technology Corp – Hardware Manual

When an internal clock is used, a serial clock is output from pin SCK₂ in synchronization with the
transmit data. After data transmission is completed, the serial clock is not output until bit STF is
set again. During this time, pin SO₂ continues to output the value of the last bit transmitted.
When an external clock is used, data is transmitted in synchronization with the serial clock input at
pin SCK₂. After data transmission is completed, an overrun occurs if the serial clock continues to
be input; no data is transmitted and the SCSR2 overrun error flag (bit ORER) is set to 1. Pin SO₂
continues to output the value of the last preceding bit. Overrun errors are not detected when both
pin CS is at the high level and PMR3 bit CS = 1.
While transmission is stopped, the output value of pin SO₂ can be changed by rewriting bit SOL in
SCSR2.
During a transmission or while waiting for CS input, the CPU cannot read or write the data buffer.
If a read instruction is executed, H'FF will be read; if a write instruction is executed, the buffer
contents will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1.
If bit CS = 1 in PMR3 and during transmission a high-level signal is detected at pin CS, the
transmit operation will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same
time bit IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to
0. Pins SCK₂ and SO₂ will go to the high-impedance state. Data transfer is not possible while bit
ABT is set to 1. It must be cleared before resuming the transfer.
Receiving: A receive operation is carried out as follows.
• Set bits SI2 and SCK2 in port mode register 3 (PMR3) to 1, designating use of the SI₂ and
SCK₂ pin functions. If necessary, set bit CS in PMR3 to select the CS pin function.
• Select the serial clock and, in the case of internal clock operation, the data gap in SCR2.
• Allocate an area to hold the received data in the serial data buffer by designating the receive
start address in the lower 5 bits of the start address register (STAR) and the receive end address
in the lower 5 bits of the end address register (EDAR).
• Set the start/busy flag (bit STF) to 1. If bit CS = 0 in PMR3, receiving starts as soon as STF is
set. If CS = 1 in PMR3, receiving starts when CS goes low.
• After receiving is completed, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and bit
STF is cleared to 0.
• Read the received data from the serial data buffer.
If an internal clock is used, a serial clock is output from pin SCK₂ when the receive operation
starts. After receiving is completed, the serial clock is not output until bit STF is set again. When
an external clock source is used, data is received in synchronization with the clock input at pin
SCK₂. After receiving is completed, an overrun occurs if the serial clock continues to be input; no
further data is received and the SCSR2 overrun error flag (bit ORER) is set to 1. Overrun errors
are not detected when both pin CS is high and bit CS = 1 in PMR3.
245