HD6473837H Datasheet, PDF (251/562 Pages) Renesas Technology Corp – Hardware Manual

10.2.4 Interrupts
SCI1 can generate an interrupt at the end of a data transfer.
When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.
SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1
(IENR1).
For further details, see 3.3, Interrupts.
10.2.5 Application Notes
When an external clock is input at pin SCK₁, and an external clock is selected for use as the clock
source bit STF in SCSR1 must first be set to 1 to start data transfer before inputting the external
clock.
10.3 SCI2
10.3.1 Overview
Serial communication interface 2 (SCI2) has a 32-bit data buffer for synchronous serial transfer of
up to 32 bytes of data in one operation.
Features
Features of SCI are listed below.
• Automatic transfer of up to 32 bytes of data
• Choice of seven internal clock sources (φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, φ/2) or an external
clock
• Interrupts requested at completion of transfer or when an error occurs
• Gaps of 56, 24, or 8 internal clock cycles can be inserted between successive bytes of
transferred data.
• Transfer can be started by chip select input.
• A strobe pulse can be output for each byte transferred.
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