HD6473837H Datasheet, PDF (309/562 Pages) Renesas Technology Corp – Hardware Manual

10.4.8 Application Notes
When using SCI3, attention should be paid to the following matters.
Relation between Bit TDRE and Writing Data to TDR: Bit TDRE in the serial status register
(SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is
automatically cleared to 0 when data is written to TDR. When SCI3 transfers data from TDR to
TSR, bit TDRE is set to 1.
Data can be written to TDR regardless of the status of bit TDRE. However, if new data is written
to TDR while TDRE is cleared to 0, assuming the data held in TDR has not yet been shifted to
TSR, it will be lost. For this reason it is advisable to confirm that bit TDRE is set to 1 before each
write to TDR and not write to TDR more than once without checking TDRE in between.
Operation when Multiple Receive Errors Occur at the Same Time: When two or more receive
errors occur at the same time, the status flags in SSR are set as shown in table 10.19. If an overrun
error occurs, data is not transferred from RSR to RDR, and receive data is lost.
Table 10.19 SSR Status Flag States and Transfer of Receive Data
SSR Status Flags
RDRF OER FER PER
*
Receive Error Status
(RSR → RDR)
1
1
0
0
×
0
0
1
0
O
0
0
0
1
O
1
1
1
0
×
1
1
0
1
×
0
0
1
1
O
1
1
1
1
×
Notation:
O: Receive data transferred from RSR to RDR
×: Receive data not transferred from RSR to RDR
Receive Data Transfer
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error
Note: * RDRF keeps the same state as before the data was received. However, if due to a late read
of received data in one frame an overrun error occurs in the next frame, RDRF is cleared to
0 when RDR is read.
Break Detection and Processing: Break signals can be detected by reading the RXD pin directly
when a framing error (FER) is detected. In the break state the input from the RXD pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state SCI3
continues to receive, so if the FER bit is cleared to 0 it will be set to 1 again.
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