HD6473837H Datasheet, PDF (220/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 2: CMFL
0
1
Description
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
Setting conditions:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1—Timer Overflow Interrupt Enable L (OVIEL): Bit 1 enables or disables TCFL overflow
interrupts.
Bit 1: OVIEL
0
1
Description
TCFL overflow interrupt disabled
TCFL overflow interrupt enabled
(initial value)
Bit 0—Counter Clear L (CCLRL): Bit 0 selects whether or not TCFL is cleared when a
compare match occurs between TCFL and OCRFL.
Bit 0: CCLRL
0
1
Description
TCFL clearing by compare match disabled
TCFL clearing by compare match enabled
(initial value)
9.5.3 Interface with the CPU
TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip
peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it
makes use of an 8-bit temporary register (TEMP).
In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte
size MOV instructions, and always access the upper byte first. Data will not be transferred
properly if only the upper byte or only the lower byte is accessed. In 8-bit mode there is no such
restriction on the order of access.
Write Access: When the upper byte is written, the upper-byte data is loaded into the TEMP
register. Next when the lower byte is written, the data in TEMP goes to the upper byte of the
register, and the lower-byte data goes directly to the lower byte of the register. Figure 9.5 shows a
TCF write operation when H'AA55 is written to TCF.
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