HD6473837H Datasheet, PDF (303/562 Pages) Renesas Technology Corp – Hardware Manual

Transmitting
processor
Receiving
processor A
(ID = 01)
Communication line
Receiving
processor B
(ID = 02)
Receiving
processor C
(ID = 03)
Receiving
processor D
(ID = 04)
Serial data
H'01
H'AA
(MPB = 1)
ID-sending cycle
(receiving processor
address)
MPB: Multiprocessor bit
(MPB = 0)
Data-sending cycle
(data sent to receiving
processor designated
by ID)
Figure 10.22 Example of Interprocessor Communication Using Multiprocessor Format
(Data H'AA Sent to Receiving Processor A)
Four communication formats are available. Parity-bit settings are ignored when a multiprocessor
format is selected. For details see table 10.16.
For a description of the clock used in multiprocessor communication, see 10.4.4, Operation in
Asynchronous Mode.
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