HD6473837H Datasheet, PDF (501/562 Pages) Renesas Technology Corp – Hardware Manual

TLC—Timer load register C
H'B5
Timer C
Bit
Initial value
Read/Write
7
TLC7
0
W
6
TLC6
0
W
5
TLC5
0
W
4
TLC4
0
W
3
TLC3
0
W
2
TLC2
0
W
1
TLC1
0
W
0
TLC0
0
W
Reload value
TCRF—Timer control register F
H'B6
Timer F
Bit
Initial value
Read/Write
7
TOLH
0
W
6
CKSH2
0
W
5
CKSH1
0
W
4
CKSH0
0
W
3
TOLL
0
W
2
CKSL2
0
W
1
CKSL1
0
W
0
CKSL0
0
W
Toggle output level H
0 Low level
1 High level
Clock select L
0 _{* *} External event (TMIF): Rising or falling edge
1 0 0 Internal clock: φ /32
1 Internal clock: φ /16
1 0 Internal clock: φ /4
1 Internal clock: φ /2
Toggle output level L
0 Low level
1 High level
Clock select H
0 _{* *} 16-bit mode selected. TCFL overflow signals are counted.
1 0 0 Internal clock: φ /32
1 Internal clock: φ /16
1 0 Internal clock: φ /4
1 Internal clock: φ /2
Note: * Don’t care
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