HD6473837H Datasheet, PDF (312/562 Pages) Renesas Technology Corp – Hardware Manual

Frame 1
Frame 2
Frame 3
Communica-
tion line
RDRF
Data 1
Data 2
Data 3
RDR
Data 1
Data 2
RDR read
A
B
RDR read
At A , data 1 is read.
At B , data 2 is read.
Figure 10.28 Relationship between Data and RDR Read Timing
To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read
once and should not be read twice or more.
When the same data must be read more than once, the data read the first time should be copied to
RAM, for example, and the copied data should be used. An alternative is to read RDR but leave a
safe margin of time before reception of the next frame is completed. In synchronous mode, all
reads of RDR should be completed before bit 7 is received. In asynchronous mode, all reads of
RDR should be completed before the stop bit is received.
Caution on Switching of SCK₃ Function: If pin SCK₃ is used as a clock output pin by SCI3 in
synchronous mode and is then switched to a general input/output pin (a pin with a different
function), the pin outputs a low level signal for half a system clock (φ) cycle immediately after it is
switched.
This can be prevented by either of the following methods according to the situation.
1. When an SCK₃ function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be
left 1. The above prevents SCK₃ from being used as a general input/output pin. To avoid an
intermediate level of voltage from being applied to SCK₃, the line connected to SCK₃ should
be pulled up to the V_CC level via a resistor, or supplied with output from an external device.
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