HD6473837H Datasheet, PDF (204/562 Pages) Renesas Technology Corp – Hardware Manual

9.3.3 Timer Operation
Interval timer Operation: When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer
B functions as an 8-bit interval timer.
Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer B is selected from seven internal clock
signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits
TMB2 to TMB0 of TMB.
After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow,
setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in interrupt enable
register 2 (IENR2), a CPU interrupt is requested.*
At overflow, TCB returns to H'00 and starts counting up again.
During interval timer operation (TMB7 = 0), when a value is set in timer load register B (TLB),
the same value is set in TCB.
Note: * For details on interrupts, see 3.3, Interrupts.
Auto-Reload Timer Operation: Setting bit TMB7 in TMB to 1 causes timer B to function as an
8-bit auto-reload timer. When a reload value is set in TLB, the same value is loaded into TCB,
becoming the value from which TCB starts its count.
After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow.
The TLB value is then loaded into TCB, and the count continues from that value. The overflow
period can be set within a range from 1 to 256 input clocks, depending on the TLB value.
The clock sources and interrupts in auto-reload mode are the same as in interval mode.
In auto-reload mode (TMB7 = 1), when a new value is set in TLB, the TLB value is also set in
TCB.
Event Counter Operation: Timer B can operate as an event counter, counting rising or falling
edges of an external event signal input at pin TMIB. External event counting is selected by setting
bits TMB2 to TMB0 in timer mode register B to all 1s (111).
When timer B is used to count external event input, bit IRQ1 in port mode register 1 (PMR1)
should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be cleared to 0 to
disable IRQ₁ interrupt requests.
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