HD6473837H Datasheet, PDF (61/562 Pages) Renesas Technology Corp – Hardware Manual

CPU state
Reset state
The CPU is initialized.
Program
execution state
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Low-power
modes
Sleep mode
Standby mode
Watch mode
Subsleep mode
Exception-
handling state
A transient state entered when the CPU changes the processing
flow due to a reset or interrupt exception handling source.
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.14 CPU Operation States
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