HD6473837H Datasheet, PDF (271/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 3—Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length in
asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop
bit is not added, so this bit is ignored.
Bit 3: STOP
Description
0
1 stop bit*¹
(initial value)
1
2 stop bits*²
Notes: 1. When data is transmitted, one 1 bit is added at the end of each transmitted character as
the stop bit.
2. When data is transmitted, two 1 bits are added at the end of each transmitted character
as the stop bits.
When data is received, only the first stop bit is checked regardless of the stop bit length. If the
second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next
character.
Bit 2—Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication
function. When the multiprocessor communication function is enabled, the parity enable (PE) and
parity mode (PM) settings are ignored. The MP bit is valid only in asynchronous mode; it should
be cleared to 0 in synchronous mode.
See 10.4.6, for details on the multiprocessor communication function.
Bit 2: MP
0
1
Description
Multiprocessor communication function disabled
Multiprocessor communication function enabled
(initial value)
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 select the clock source for the built-
in baud rate generator. A choice of φ/64, φ/16, φ/4, or φ is made in these bits.
See 8, Bit rate register (BRR), below for information on the clock source and bit rate register
settings, and their relation to the baud rate.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
(initial value)
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