HD6473837H Datasheet, PDF (491/562 Pages) Renesas Technology Corp – Hardware Manual

EDAR—End address register
Bit
7
6
—
—
Initial value
1
1
Read/Write
—
—
H'A5
SCI2
5
4
3
2
1
0
—
EDA4 EDA3 EDA2 EDA1 EDA0
1
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
Transfer end address in range from
H'FF80 to H'FF9F
SCR2—Serial control register 2
H'A6
SCI2
Bit
7
6
5
4
3
2
1
0
—
—
—
GAP1 GAP0 CKS2 CKS1 CKS0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W R/W R/W R/W R/W
Clock Select (CKS2 to CKS0)
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Pin SCK ₂
0
0
0 SCK ₂ output
1
1
0
1
1
0
0
1
1
0
1 SCK ₂ input
Prescaler
Clock Source Division
Prescaler S φ/256
φ /64
φ /32
φ /16
φ /8
φ /4
φ /2
External clock —
Serial Clock Cycle
φ = 5 MHz φ = 2.5 MHz
51.2 µs
102.4 µs
12.8 µs
25.6 µs
6.4 µs
12.8 µs
3.2 µs
6.4 µs
1.6 µs
3.2 µs
0.8 µs
1.6 µs
—
0.8 µs
—
—
Gap select
0 0 No gaps between bytes
1 A gap of 8 clock cycles is inserted between bytes
1 0 A gap of 24 clock cycles is inserted between bytes
1 A gap of 56 clock cycles is inserted between bytes
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