HD6473837H Datasheet, PDF (276/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 5—Overrun Error (OER): Bit 5 is a status flag indicating that an overrun error has occurred
during data receiving.
Bit 5: OER Description
0
Indicates that data receiving is in progress or has been completed*¹ (initial value)
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
1
Indicates that an overrun error occurred in data receiving*²
Setting condition:
When data receiving is completed while RDRF is set to 1
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and
keeps its previous state.
2. RDR keeps the data received prior to the overrun; data received after that is lost. While
OER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
Bit 4—Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred
during asynchronous receiving.
Bit 4: FER
Description
0
Indicates that data receiving is in progress or has been completed*¹ (initial value)
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1
Indicates that a framing error occurred in data receiving
Setting condition:
The stop bit at the end of receive data is checked for a value of 1 and found to be
0*²
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and
keeps its previous state.
2. When two stop bits are used only the first stop bit is checked, not the second. When a
framing error occurs, receive data is transferred to RDR but RDRF is not set. While
FER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
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