HD6473837H Datasheet, PDF (246/562 Pages) Renesas Technology Corp – Hardware Manual

Serial Control/Status Register 1 (SCSR1)
Bit
7
6
5
4
3
2
1
0
—
SOL ORER
—
—
—
—
STF
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W R/(W)* —
—
—
R/W
R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR1 is an 8-bit read/write register indicating operation status and error status.
Upon reset, SCSR1 is initialized to H'80.
Bit 7—Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified.
Bit 6—Extended Data Bit (SOL): Bit 6 sets the SO₁ output level. When read, SOL returns the
output level at the SO₁ pin. After completion of a transmission, SO₁ continues to output the value
of the last bit of transmitted data. The SO₁ output can be changed by writing to SOL before or
after a transmission. The SOL bit setting remains valid only until the start of the next transmission.
To control the level of the SO₁ pin after transmission ends, it is necessary to write to the SOL bit at
the end of each transmission. Do not write to this register while transmission is in progress,
because that may cause a malfunction.
Bit 6: SOL
0
1
Description
Read: SO₁ pin output level is low
Write: SO₁ pin output level changes to low
Read: SO₁ pin output level is high
Write: SO₁ pin output level changes to high
(initial value)
Bit 5—Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the
occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1
indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be
superimposed on the normal serial clock, incorrect data may be transferred.
Bit 5: ORER
0
1
Description
Clearing conditions:
After reading ORER = 1, cleared by writing 0 to ORER
(initial value)
Setting conditions:
Set if a clock pulse is input after transfer is complete, when an external clock is
used
229