HD6473837H Datasheet, PDF (119/562 Pages) Renesas Technology Corp – Hardware Manual

5.4.2 Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, IRQ₀, WKP₀ to WKP₇) or by a input at the RES
pin.
Clearing by Interrupt: Watch mode is cleared when an interrupt is requested. The mode to which
a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both
LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and
MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive
mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2–STS0 has
elapsed, a stable clock signal is supplied to the entire chip, and interrupt exception handling starts.
Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
Clearing by RES Input: Clearing by RES pin is the same as for standby mode; see 5.3.2,
Clearing Standby Mode.
5.4.3 Oscillator Settling Time after Watch Mode is Cleared
The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
5.5 Subsleep Mode
5.5.1 Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1.
In subsleep mode, operation of on-chip peripheral modules other than timer A, timer C, timer G,
and the LCD controller is halted. As long as a minimum required voltage is applied, the contents
of CPU registers and some registers of the on-chip peripheral modules, and the on-chip RAM
contents, are retained. I/O ports keep the same states as before the transition.
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