HD6473837H Datasheet, PDF (274/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 2—Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end
interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit end interrupt (TEI) disabled
(initial value)
1
Transmit end interrupt (TEI) enabled*
Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit
end bit (TEND) to 0, or by clearing bit TEIE to 0.
Bits 1 and 0—Clock Enable 1, 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enable
or disable clock output at pin SCK₃. The combination of bits CKE1 and CKE0 determines whether
pin SCK₃ is a general I/O port, a clock output pin, or a clock input pin.
Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal
clock (CKE1 = 0). This bit is invalid in synchronous mode or when using an external clock
(CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits
CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR).
See table 10.9 in 10.4.3, Operation, for details on clock source selection.
Bit 1: CKE1 Bit 0: CKE0 Communication Mode Clock Source
0
0
Asynchronous
Internal clock
Synchronous
Internal clock
0
1
Asynchronous
Internal clock
Synchronous
Reserved
1
0
Asynchronous
External clock
Synchronous
External clock
1
1
Asynchronous
Reserved
Synchronous
Reserved
Notes: 1. Initial value
2. A clock is output with the same frequency as the bit rate.
3. Input a clock with a frequency 16 times the bit rate.
SCK₃ Pin Function
I/O port*¹
Serial clock output*¹
Clock output*²
Reserved
Clock input*³
Serial clock input
Reserved
Reserved
Serial Status Register (SSR)
Bit
7
6
5
TDRE RDRF OER
Initial value
1
0
0
Read/Write R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written for flag clearing.
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPBR
0
R
0
MPBT
0
R/W
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