HD6433832S Datasheet, PDF (90/560 Pages) Renesas Technology Corp – single-chip microcomputers

Bit 0—Timer B Interrupt Request Flag (IRRTB)
Bit 0: IRRTB
0
1
Description
Clearing conditions:
When IRRTB = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When the timer B counter value overflows (goes from H'FF to H'00)
Wakeup Interrupt Request Register (IWPR)
Bit
Initial value
Read/Write
7
IWPF7
0
R/W*
6
IWPF6
0
R/W*
5
IWPF5
0
R/W*
4
IWPF4
0
R/W*
3
IWPF3
0
R/W*
2
IWPF2
0
R/W*
1
IWPF1
0
R/W*
0
IWPF0
0
R/W*
Note: * Only a write of 0 for flag clearing is possible.
IWPR
is
an
8-bit
read/write
register,
in
which
the
corresponding
bit
is
set
to
1
when
pins
WKP
7
to
WKP₀ are set to wakeup input and a pin receives a falling edge input. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bits 7 to 0—Wakeup Interrupt Request Flags (WKPF7 to WKPF0)
Bit n: IWPFn
0
1
Description
Clearing conditions:
When IWPFn = 1, it is cleared by writing 0 to IWPFn
Setting conditions:
IWPFn is set when pin WKP_n is set to wakeup interrupt input, and a falling edge
input is detected at the pin
(n = 7 to 0)
3.3.3 External Interrupts
There are 13 external interrupts, WKP₀ to WKP₇ and IRQ₀ to IRQ₄.
Interrupts WKP₀ to WKP₇: Interrupts WKP₀ to WKP₇ are requested by falling edge inputs at
pins WKP₀ to WKP₇. When these pins are designated as WKP₀ to WKP₇ pins in port mode register
5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request
register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by
clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR
I bit to 1.
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