HD6433832S Datasheet, PDF (309/560 Pages) Renesas Technology Corp – single-chip microcomputers

The receive margin in asynchronous mode can therefore be derived from the following equation.
M = {(0.5 – 1/2N) – (D – 0.5) / N – (L – 0.5) F} × 100% ............................ Equation (1)
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0.5 to 1)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency error
In equation (1), if F (absolute value of clock frequency error) = 0 and D (clock duty cycle) = 0.5,
the receive margin is 46.875% as given by equation (2) below.
When D = 0.5 and F = 0,
M = {0.5 – 1/(2 × 16)} × 100% = 46.875% ................................................ Equation (2)
This value is theoretical. In actual system designs a margin of from 20 to 30 percent should be
allowed.
Relationship between Bit RDRF and Reading RDR: While SCI3 is receiving, it checks the
RDRF flag. When a frame of data has been received, if the RDRF flag is cleared to 0, data
receiving ends normally. If RDRF is set to 1, an overrun error occurs.
RDRF is automatically cleared to 0 when the contents of RDR are read. If RDR is read more than
once, the second and later reads will be performed with RDRF cleared to 0. While RDRF is 0, if
RDR is read when reception of the next frame is just ending, data from the next frame may be
read. This is illustrated in figure 10.28.
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