HD6433832S Datasheet, PDF (262/560 Pages) Renesas Technology Corp – single-chip microcomputers

During a transfer or while waiting for CS input, the CPU cannot read or write the data buffer. If a
read instruction is executed, H'FF will be read; if a write instruction is executed the buffer contents
will not change. In either case the wait flag (bit WT) in SCSR2 will be set.
If bit CS = 1 in PMR3 and during the transfer a high-level signal is detected at pin CS, the transfer
will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit IRRS2 in
interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins SCK₂ and
SO₂ will go to the high-impedance state. Data transfer is not possible while bit ABT is set to 1. It
must be cleared before resuming the transfer.
10.3.4 Interrupts
SCI2 can generate interrupts when a transfer is completed or when a transfer is aborted by CS.
These interrupts have the same vector address.
When the above conditions occur, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1. SCI2
interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 2 (IENR2).
For further details, see 3.3, Interrupts.
When a transfer is aborted by CS, an overrun error occurs, or a read or write of the serial data
buffer is attempted during a transfer or while waiting for CS input, the ABT, ORER, or WT bit in
SCSR2 is set to 1. These bits can be used to determine the cause of the error.
10.3.5 Application Notes
When an external clock is input at pin SCK₂, and an external clock is selected for use as the clock
source bit STF in SCSR2 must first be set to 1 to start data transfer before inputting the external
clock.
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