HD6433832S Datasheet, PDF (333/560 Pages) Renesas Technology Corp – single-chip microcomputers

Bit 3:
CKS3
Bit 2:
CKS2
Bit 1:
CKS1
Bit 0:
CKS0
Clock
Frame Frequency*³
φ = 5 MHz
φ = 625 kHz*¹
0
*
0
0
φ_W
0
*
0
1
φ_W/2
0
*
1
*
φ_W/4
1
0
0
0
φ/2
128 Hz*²
64 Hz
32 Hz
—
128 Hz*2
64 Hz
32 Hz
610 Hz
1
0
0
1
φ/4
—
305 Hz
1
0
1
0
φ/8
—
153 Hz
1
0
1
1
φ/16
610 Hz
76.3 Hz
1
1
0
0
φ/32
305 Hz
38.1 Hz
1
1
0
1
φ/64
153 Hz
—
1
1
1
0
φ/128
76.3 Hz
—
1
1
1
1
φ/256
38.1 Hz
—
Notes: * Don’t care
1. Frame frequency in active (medium-speed) mode when φ = 5 MHz
2. Only the upper 32 bytes of the display RAM are used.
3. When a duty cycle of 1/3 is chosen, the frame frequency will be 4/3 times the
frequencies shown in the above table.
13.3 Operation
13.3.1 Settings Prior to LCD Display
Various decisions related to hardware and software must be made before using the LCD
controller/driver with an LCD display. The settings are described below.
Hardware Settings
• Use at 1/2 duty
To use at 1/2 duty, connect pins V₂ and V₃ as shown in figure 13.2.
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