HD6433832S Datasheet, PDF (248/560 Pages) Renesas Technology Corp – single-chip microcomputers

• Read the received data from SDRL and SDRU, as follows.
 8-bit transfer mode: SDRL
 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
• After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Simultaneous transmit/receive: A simultaneous transmit/receive operation is carried out as
follows.
• Set bits SO1, SI1, and SCK1 in PMR3 to 1 so that the respective pins function as SO₁, SI₁, and
SCK₁. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output
at pin SO₁.
• Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous
transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes
the internal state of SCI1.
• Write transmit data in SDRL and SDRU, as follows.
 8-bit transfer mode: SDRL
 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
• Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO₁.
Receive data is input at pin SI₁.
• After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1.
• Read the received data from SDRL and SDRU, as follows.
 8-bit transfer mode: SDRL
 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
When an internal clock is used, a serial clock is output from pin SCK₁ in synchronization with the
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO₁ continues to output the value of the last bit
transmitted.
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK₁. After data transmission and reception are complete, an overrun occurs if
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO₁ can be changed by rewriting bit SOL in
SCSR1.
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