HD6433832S Datasheet, PDF (111/560 Pages) Renesas Technology Corp – single-chip microcomputers

5.1.1 System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3 System Control Register
Name
System control register 1
System control register 2
Abbreviation
SYSCR1
SYSCR2
R/W
Initial Value
Address
R/W
H'07
H'FFF0
R/W
H'E0
H'FFF1
System Control Register 1 (SYSCR1)
Bit
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 LSON
—
—
—
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
—
—
—
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Bit 7—Software Standby (SSBY): This bit designates transition to standby mode or watch mode.
Bit 7: SSBY
0
1
Description
• When a SLEEP instruction is executed in active mode, a transition is made
to sleep mode
(initial value)
• When a SLEEP instruction is executed in subactive mode, a transition is
made to subsleep mode.
• When a SLEEP instruction is executed in active mode, a transition is made
to standby mode or watch mode.
• When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from standby mode or
watch mode to active mode due to an interrupt. The designation should be made according to the
clock frequency so that the waiting time is at least 10 ms.
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