HD6433832S Datasheet, PDF (206/560 Pages) Renesas Technology Corp – single-chip microcomputers

Bits 4 and 3—Reserved Bits: Bits 4 and 3 are reserved; they are always read as 1, and cannot be
modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0): Bits 2 to 0 select the clock input to TCC. For
external clock counting, either the rising or falling edge can be selected.
Bit 2: TMC2 Bit 1: TMC1 Bit 0: TMC0 Description
0
0
0
Internal clock: φ/8192
(initial value)
1
Internal clock: φ/2048
1
0
Internal clock: φ/512
1
Internal clock: φ/64
1
0
0
Internal clock: φ/16
1
Internal clock: φ/4
1
0
Internal clock: φ_W/4
1
External event (TMIC): rising or falling edge*
Note: * The edge of the external event signal is selected by bit IEG2 in the IRQ edge select register
(IEGR). See 3.3.2, for details on the IRQ edge select register. Be sure to set bit IRQ2 in
port mode register 1 (PMR1) to 1 before setting bits TMC2 to TMC0 to 111.
Timer Counter C (TCC)
Bit
Initial value
Read/Write
7
TCC7
0
R
6
TCC6
0
R
5
TCC5
0
R
4
TCC4
0
R
3
TCC3
0
R
2
TCC2
0
R
1
TCC1
0
R
0
TCC0
0
R
TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or
external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0
in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to
H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.
TCC is allocated to the same address as timer load register C (TLC).
Upon reset, TCC is initialized to H'00.
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