HD6433832S Datasheet, PDF (494/560 Pages) Renesas Technology Corp – single-chip microcomputers

SSR—Serial status register
H'AC
SCI3
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
OER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPBR
0
R
0
MPBT
0
R/W
Multiprocessor bit receive
0 Indicates reception of data in which the multiprocessor bit is 0
1 Indicates reception of data in which the multiprocessor bit is 1
Multiprocessor bit transmit
0 The multiprocessor bit in transmit data is 0
1 The multiprocessor bit in transmit data is 1
Transmit end
0 Indicates that transmission is in progress
[Clearing conditions] After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
1 Indicates that a transmission has ended
[Setting conditions] When bit TE in serial control register 3 (SCR3) is 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
Parity error
0 Indicates that data receiving is in progress or has been completed
[Clearing conditions] After reading PER = 1, cleared by writing 0
1 Indicates that a parity error occurred in data receiving
[Setting conditions] When the sum of 1s in received data plus the parity bit does not match
the parity mode bit (PM) setting in the serial mode register (SMR)
Framing error
0 Indicates that data receiving is in progress or has been completed
[Clearing conditions] After reading FER = 1, cleared by writing 0
1 Indicates that a framing error occurred in data receiving
[Setting conditions] The stop bit at the end of receive data is checked and found to be 0
Overrun error
0 Indicates that data receiving is in progress or has been completed
[Clearing conditions] After reading OER = 1, cleared by writing 0
1 Indicates that an overrun error occurred in data receiving
[Setting conditions] When data receiving is completed while RDRF is set to 1
Receive data register full
0 Indicates there is no receive data in RDR
[Clearing conditions] After reading RDRF = 1, cleared by writing 0.
When data is read from RDR by an instruction.
1 Indicates that there is receive data in RDR
[Setting conditions] When receiving ends normally, with receive data transferred from RSR to RDR
Transmit data register empty
0 Indicates that transmit data written to TDR has not been transferred to TSR
[Clearing conditions] After reading TDRE = 1, cleared by writing 0.
When data is written to TDR by an instruction.
1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR
[Setting conditions] When bit TE in serial control register 3 (SCR3) is 0.
When data is transferred from TDR to TSR.
Note: * Only a write of 0 for flag clearing is possible.
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