HD6433832S Datasheet, PDF (502/560 Pages) Renesas Technology Corp – single-chip microcomputers

TMG—Timer mode register G
H'BC
Timer G
Bit
Initial value
Read/Write
7
OVFH
0
R/(W)*
6
OVFL
0
R/(W)*
5
OVIE
0
R/W
4
IIEGS
0
R/W
3
2
CCLR1 CCLR0
0
0
R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select
0 0 Internal clock: φ /64
1 Internal clock: φ /32
1 0 Internal clock: φ /2
Counter clear
1 Internal clock: φ _W/2
0 0 TCG is not cleared
1 TCG is cleared at the falling edge of the input capture signal
1 0 TCG is cleared at the rising edge of the input capture signal
1 TCG is cleared at both edges of the input capture signal
Input capture interrupt edge select
0 Interrupts are requested at the rising edge of the input capture signal
1 Interrupts are requested at the falling edge of the input capture signal
Timer overflow interrupt enable
0 TCG overflow interrupt disabled
1 TCG overflow interrupt enabled
Timer overflow flag L
0 [Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1 [Setting condition]
When the value of TCG goes from H'FF to H'00
Timer overflow flag H
0 [Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1 [Setting condition]
When the value of TCG goes from H'FF to H'00
Note: * Only a write of 0 for flag clearing is possible.
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