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| HD6433832S Datasheet, PDF (381/560 Pages) Renesas Technology Corp – single-chip microcomputers | |||
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14.5.3 AC Characteristics
Table 14.18 lists the control signal timing, and tables 14.19 and 14.20 list the serial interface
timing of the H8/3832S, H8/3833S, and H8/3834S (wide temperature range (I-spec) version).
Table 14.18 Control Signal Timing of H8/3832S, H8/3833S, and H8/3834S (Wide
Temperature Range (I-Spec) Version)
VCC = 2.5 V to 5.5 V, AVCC = 2.5 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = â40°C to +85°C, including
subactive mode, unless otherwise specified.
Item
Applicable
Symbol Pins
Min Typ Max Unit Test Condition
Reference
Figure
System clock
fOSC
oscillation frequency
OSC1, OSC2 2.0 â
2.0 â
10.0 MHz VCC = 4.0 V to 5.5 V
5.0
OSC clock (ÏOSC)
cycle time
tOSC
OSC1, OSC2 100.0 â
1000.0 ns VCC = 4.0 V to 5.5 V 1
200.0 â
1000.0
Figure 14.1
System clock (Ï)
tcyc
2â
16
tOSC
1
cycle time
ââ
2000.0 ns
Subclock oscillation fW
frequency
X1, X2
â 32.768 â kHz
Watch clock (Ïw) cycle tW
time
X1, X2
â 30.5 â µs
Subclock (ÏSUB) cycle tsubcyc
2â
8
tW
2
time
Instruction cycle time
Oscillation stabilization trc
time (crystal oscillator)
2â
OSC1, OSC2 â â
ââ
ââ
â
tcyc
tsubcyc
40.0 ms VCC = 4.0 V to 5.5 V
60.0
VCC = 2.7 V to 5.5 V
100.0
Oscillation stabilization trc
time
X1, X2
ââ
2.0 s
External clock high
tCPH
width
OSC1
40.0 â
80.0 â
â ns VCC = 4.0 V to 5.5 V Figure 14.1
â
External clock low
tCPL
OSC1
width
40.0 â
80.0 â
â ns VCC = 4.0 V to 5.5 V Figure 14.1
â
External clock rise time tCPr
ââ
ââ
15.0 ns
20.0
VCC = 4.0 V to 5.5 V Figure 14.1
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
366
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