HD6433832S Datasheet, PDF (116/560 Pages) Renesas Technology Corp – single-chip microcomputers

5.3.4 Transition to Standby Mode and Port Pin States
The system goes from active (high-speed or medium-speed) mode to standby mode when a
SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared
to 0, and bit TMA3 in TMA is cleared to 0. Port pins (except those with their MOS pull-up turned
on) enter high-impedance state when the transition to standby mode is made. This timing is shown
in figure 5.2.
φ
Internal
data bus
SLEEP instruction fetch
Next instruction fetch
SLEEP instruction
execution
Internal
processing
Port pins
Output
Active (high-speed or medium-speed) mode
High-impedance
Standby mode
Figure 5.2 Transition to Standby Mode and Port Pin States
5.4 Watch Mode
5.4.1 Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules other than timer A and the LCD
controller is halted. The LCD controller can be selected to operate or to halt. As long as a
minimum required voltage is applied, the contents of CPU registers and some registers of the on-
chip peripheral modules, and the on-chip RAM contents, are retained. I/O ports keep the same
states as before the transition.
101