HD6433832S Datasheet, PDF (290/560 Pages) Renesas Technology Corp – single-chip microcomputers

SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10.16. Next, TDRE is checked as the stop bit is being transmitted.
If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of
the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent
the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3
is set to 1.
Figure 10.13 shows a typical operation in asynchronous transmission mode.
Serial
data
Start
bit
Transmit
data
Parity Stop Start
bit bit bit
Transmit
data
Parity Stop Mark
bit bit state
1 0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1 1
1 frame
1 frame
TDRE
TEND
SCI3 TXI request TDRE cleared to 0
operation
User
processing
Write data in TDR
TXI request
TEI request
Figure 10.13 Typical Transmit Operation in Asynchronous Mode
(8-Bit Data, Parity Bit Added, and 1 Stop Bit)
Receiving: Figure 10.14 shows a typical flow chart for receiving serial data. After SCI3
initialization, follow the procedure below.
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