HD6433832S Datasheet, PDF (227/560 Pages) Renesas Technology Corp – single-chip microcomputers

Register Configuration
Table 9.15 shows the register configuration of timer G.
Table 9.15 Timer G Registers
Name
Timer mode register G
Timer counter G
Input capture register GF
Input capture register GR
Abbrev.
R/W
TMG
R/W
TCG
—
ICRGF
R
ICRGR
R
Initial Value
H'00
H'00
H'00
H'00
Address
H'FFBC
—
H'FFBD
H'FFBE
9.6.2 Register Descriptions
Timer Counter G (TCG)
Bit
Initial value
Read/Write
7
TCG7
0
—
6
TCG6
0
—
5
TCG5
0
—
4
TCG4
0
—
3
TCG3
0
—
2
TCG2
0
—
1
TCG1
0
—
0
TCG0
0
—
Timer counter G (TCG) is an 8-bit up-counter which is incremented by an input clock. The input
clock signal is selected by bits CKS1 and CKS0 in timer mode register G (TMG).
To use TCG as an input capture timer, set bit TMIG to 1 in PMR1; to use TCG as an interval
timer, clear bit TMIG to 0.* When TCG is used as an input capture timer, the TCG value can be
cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on
settings in TMG.
When TCG overflows (goes from H'FF to H'00), if the timer overflow interrupt enable bit (OVIE)
is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit
IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on
interrupts are given in 3.3, Interrupts.
TCG cannot be read or written by the CPU.
Upon reset, TCG is initialized to H'00.
Note: * An input capture signal may be generated when TMIG is rewritten.
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