HD6433832S Datasheet, PDF (229/560 Pages) Renesas Technology Corp – single-chip microcomputers

Timer Bode Register G (TMG)
Bit
Initial value
Read/Write
7
OVFH
0
R/W*
6
OVFL
0
R/W*
5
OVIE
0
R/W
Note: * Only 0 can be written, to clear flag.
4
IIEGS
0
R/W
3
CCLR1
0
R/W
2
CCLR0
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TMG is an 8-bit read/write register. It controls the choice of four input clocks, counter clear
selection, and edge selection for input capture interrupt requests. It also indicates overflow status
and enables or disables overflow interrupt requests.
Upon reset, TMG is initialized to H'00.
Bit 7—Timer Overflow Flag H (OVFH): Bit 7 is a status flag indicating that TCG overflowed
(from H'FF to H'00) when the input capture signal was high. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 7: OVFH
0
1
Description
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting conditions:
Set when the value of TCG overflows from H'FF to H'00
(initial value)
Bit 6—Timer Overflow Flag L (OVFL): Bit 6 is a status flag indicating that TCG overflowed
(from H'FF to H'00) when the input capture signal was low, or in interval timer operation. This
flag is set by hardware and cleared by software. It cannot be set by software.
Bit 6: OVFL
0
1
Description
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting conditions:
Set when the value of TCG overflows from H'FF to H'00
(initial value)
Bit 5—Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables TCG overflow
interrupts.
Bit 5: OVIE
0
1
Description
TCG overflow interrupt disabled
TCG overflow interrupt enabled
(initial value)
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