HD6433832S Datasheet, PDF (114/560 Pages) Renesas Technology Corp – single-chip microcomputers

5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
The system goes from active mode to sleep mode when a SLEEP instruction is executed while the
SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU
operation is halted but the on-chip peripheral functions other than PWM are operational. The CPU
register contents are retained.
5.2.2 Clearing Sleep Mode
Sleep mode is cleared by an interrupt (timer A, timer B, timer C, timer F, timer G, IRQ₀ to IRQ₄,
WKP₀ to WKP₇, SCI1, SCI2, SCI3, A/D converter) or by input at the RES pin.
Clearing by Interrupt: When an interrupt is requested, sleep mode is cleared and interrupt
exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in
SYSCR2, or active (medium-speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
Clearing by RES Input: When the RES pin goes low, the CPU goes into the reset state and sleep
mode is cleared.
5.3 Standby Mode
5.3.1 Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer
register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and
on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied,
the contents of CPU registers and some on-chip peripheral registers, and data in the on-chip RAM,
are retained. Data in the on-chip RAM will be retained as long as the specified RAM data
retention voltage is supplied. The I/O ports go to the high-impedance state.
99