HD6433832S Datasheet, PDF (118/560 Pages) Renesas Technology Corp – single-chip microcomputers

5.5.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer G, IRQ₀ to IRQ₄, WKP₀ to
WKP₇) or by a low input at the RES pin.
Clearing by Interrupt: When an interrupt is requested, subsleep mode is cleared and interrupt
exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
Clearing by RES Input: Clearing by RES pin is the same as for standby mode; see 5.3.2,
Clearing Standby Mode.
5.6 Subactive Mode
5.6.1 Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, IRQ₀, or WKP₀ to WKP₇ interrupt is
requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is
entered if a timer A, timer C, timer G, IRQ₀ to IRQ₄, or WKP₀ to WKP₇ interrupt is requested.
A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
5.6.2 Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a input at the RES pin.
Clearing by SLEEP Instruction: If a SLEEP instruction is executed while the SSBY bit in
SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode
is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and
TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see
5.8, Direct Transfer, below.
Clearing by RES Pin: Clearing by RES pin is the same as for standby mode; see Clearing by
RES pin in section 5.3.2, Clearing Standby Mode.
5.6.3 Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φ_W/2, φ_W/4, and φ_W/8.
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