HD6433832S Datasheet, PDF (283/560 Pages) Renesas Technology Corp – single-chip microcomputers

Table 10.14 SMR and SCR3 Settings and Clock Source Selection
SMR
Bit 7:
COM
0
1
0
1
1
SCR3
Bit 1: Bit 0:
CKE1 CKE0
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
Mode
Asynchronous
mode
Synchronous
mode
Reserved
Transmit/Receive Clock
Clock
Source
Internal
Pin SCK₃ Function
I/O port (SCK₃ function not used)
Outputs clock with same frequency as
bit rate
External Clock should be input with frequency
16 times the desired bit rate
Internal Outputs a serial clock
External Inputs a serial clock
(illegal settings)
Continuous Transmit/Receive Operation Using Interrupts: Continuous transmit and receive
operations are possible with SCI3, using the RXI or TXI interrupts. Table 10.15 explains this use
of these interrupts.
Table 10.15 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
Flag
RDRF
RIE
TDRE
TIE
TEND
TEIE
Interrupt Conditions
Remarks
When serial data is received normally
and receive data is transferred from
RSR to RDR, RDRF is set to 1. If RIE
is 1 at this time, RXI is enabled and an
interrupt occurs. (See figure
10.8 (a).)
The RXI interrupt handler routine
should read the receive data from
RDR and clear RDRF to 0.
Continuous receiving is possible if
these operations are completed
before the next data has been
completely received in RSR.
When TSR empty (previous trans-
mission complete) is detected and the
transmit data set in TDR is transferred
to TSR, TDRE is set to 1. If TIE is 1 at
this time, TXI is enabled and an
interrupt occurs. (See figure 10.8 (b).)
The TXI interrupt handler routine
should write the next transmit data
to TDR and clear TDRE to
0.Continuous transmission is
possible if these operations are
completed before the data
transferred to TSR has been
completely transmitted.
When the last bit of the TSR transmit
character has been sent, if TDRE is 1,
then 1 is set in TEND. If TEIE is 1 at
this time, TEI is enabled and an
interrupt occurs. (See figure 10.8 (c).)
TEI indicates that, when the last bit
of the TSR transmit character was
sent, the next transmit data had
not been written to TDR.
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