HD6433832S Datasheet, PDF (112/560 Pages) Renesas Technology Corp – single-chip microcomputers

Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description
0
0
0
Wait time = 8,192 states
1
Wait time = 16,384 states
1
0
Wait time = 32,768 states
1
Wait time = 65,536 states
1
*
*
Wait time = 131,072 states
Note: * Don’t care
(initial value)
Bit 3—Low Speed on Flag (LSON): This bit chooses the system clock (φ) or subclock (φ_SUB) as
the CPU operating clock when watch mode is cleared. The resulting operation mode depends on
the combination of other control bits and interrupt input.
Bit 3: LSON
0
1
Description
The CPU operates on the system clock (φ)
The CPU operates on the subclock (φ_SUB)
(initial value)
Bits 2 to 0—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
—
—
— NESEL DTON MSON SA1
SA0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
Bit 4—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal (φ_W) generated by the subclock pulse generator is sampled, in
relation to the oscillator clock (φ_OSC) generated by the system clock pulse generator. When φ_OSC =
2 to 10 MHz, clear NESEL to 0.
Bit 4: NESEL
0
1
Description
Sampling rate is φ_OSC/16
Sampling rate is φ_OSC/4
(initial value)
97