HD6433832S Datasheet, PDF (88/560 Pages) Renesas Technology Corp – single-chip microcomputers

Interrupt Request Register 2 (IRR2)
Bit
Initial value
Read/Write
7
IRRDT
0
R/W*
6
IRRAD
0
R/W*
5
IRRS2
0
R/W*
4
IRRTG
0
R/W*
3
2
IRRTFH IRRTFL
0
0
R/W* R/W*
1
IRRTC
0
R/W*
0
IRRTB
0
R/W*
Note: * Only a write of 0 for flag clearing is possible.
IRR2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct
transfer, A/D converter, SCI2, timer G, timer FH, timer FL, timer C, or timer B interrupt is
requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to
write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT
0
1
Description
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When DTON = 1 and a direct transfer is made immediately after a SLEEP
instruction is executed
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD
0
1
Description
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
Setting conditions:
When A/D conversion is completed and ADSF is reset
(initial value)
Bit 5—SCI2 Interrupt Request Flag (IRRS2)
Bit 5: IRRS2
0
1
Description
Clearing conditions:
When IRRS2 = 1, it is cleared by writing 0
Setting conditions:
When an SCI2 transfer is completed or aborted
(initial value)
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