HD6433832S Datasheet, PDF (79/560 Pages) Renesas Technology Corp – single-chip microcomputers

Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
When system power is turned on or off, the RES pin should be held low.
Figures 3.1 and 3.2 show the reset sequence.
Reset cleared
RES
MD0
φ
High
Program initial
Vector fetch Internal ^{instruction prefetch}
processing
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence (when MD0 Pin is High)
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