HD6433832S Datasheet, PDF (113/560 Pages) Renesas Technology Corp – single-chip microcomputers

Bit 3—Direct Transfer on Flag (DTON): This bit designates whether or not to make direct
transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP
instruction is executed. The mode to which the transition is made after the SLEEP instruction is
executed depends on a combination of this and other control bits.
Bit 3: DTON
0
1
Description
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode, watch mode, or sleep mode.
(initial value)
When a SLEEP instruction is executed in subactive mode, a transition is made
to watch mode or subsleep mode.
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in active (medium-speed) mode, a
direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0,
and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON =
0, and MSON = 1.
Bit 2—Medium Speed on Flag (MSON): After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed) mode.
Bit 2: MSON
0
1
Description
Operation is in active (high-speed) mode
Operation is in active (medium-speed) mode
(initial value)
Bits 1 and 0—Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock
rate (φ_W/2, φ_W/4, or φ_W/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.
Bit 1: SA1
Bit 0: SA0
0
0
1
1
*
Note: * Don’t care
Description
φ_W/8
φ_W/4
φ_W/2
(initial value)
98