HD6433832S Datasheet, PDF (222/560 Pages) Renesas Technology Corp – single-chip microcomputers

TCF Count Timing: TCF is incremented by each pulse of the input clock (internal or external
clock).
• Internal clock
The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four
internal clock signals divided from the system clock (φ), namely, φ/32, φ/16, φ/4, or φ/2.
• External clock
External clock input is selected by clearing bit CKSL2 to 0 in TCRF. Either rising or falling
edges of the clock input can be counted. The edge of an external event is selected by bit IEG3
in the interrupt controller’s IEGR register. An external event pulse width of at least two system
clock (φ) cycles is necessary for correct operation of the counter.
TMOFH and TMOFL Output Timing: The outputs at pins TMOFH and TMOFL are the values
set in bits TOLH and TOLL in TCRF. When a compare match occurs, the output value is inverted.
Figure 9.7 shows the output timing.
ø
TMIF
(when IEG3 = 1)
Count input
clock
TCF
N
N+1
N
N+1
OCRF
N
N
Compare match
signal
TMOFH, TMOFL
Figure 9.7 TMOFH, TMOFL Output Timing
TCF Clear Timing: TCF can be cleared at compare match with OCRF.
Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows (goes from
H'FFFF to H'0000).
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