HD6433832S Datasheet, PDF (231/560 Pages) Renesas Technology Corp – single-chip microcomputers

Sampling clock
Input capture
signal
C
DQ
latch
C
DQ
latch
C
DQ
latch
C
DQ
latch
C
DQ
latch
Match
detection
circuit
Noise
canceller
output
∆t
Sampling clock
∆ t: Selected by bits CKS1, CKS0.
Figure 9.9 Block Diagram of Noise Canceller Circuit
The noise canceller consists of five latch circuits connected in series, and a match detection
circuit. When the noise canceller function is disabled (NCS = 0), the system clock is selected as
the sampling clock. When the noise canceller is enabled (NCS = 1), the internal clock selected by
bits CKS1 and CKS0 in TMG becomes the sampling clock. The input signal is sampled at the
rising edge of this clock pulse. Data is considered correct when the outputs of all five latch circuits
match. If they do not match, the previous value is retained. Upon reset, the noise canceller output
is initialized after the falling edge of the input capture signal has been sampled five times.
Accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times
greater than the sampling clock will be recognized as input capture signals.
If the noise canceller circuit is not used, the input capture signal pulse width must be at least 2φ or
2φ_SUB in order to ensure proper input capture operation.
Note: * Rewriting the NCS bit may cause an internal input capture signal to be generated.
Figure 9.10 shows a typical timing diagram for the noise canceller circuit. In this example, a high-
level input at the input capture pin is rejected as noise because its pulse width is less than five
sampling clock φ cycles.
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