HD6433832S Datasheet, PDF (115/560 Pages) Renesas Technology Corp – single-chip microcomputers

5.3.2 Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ₀, IRQ₁, WKP₀ to WKP₇) or by input at the RES pin.
Clearing by Interrupt: When an interrupt is requested, the system clock pulse generator starts.
After the time set in bits STS2–STS0 in SYSCR1 has elapsed, a stable system clock signal is
supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts.
Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-
speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
Clearing by RES Input: When the RES pin goes low, the system clock pulse generator starts.
After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset
exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse generator
output stabilizes.
5.3.3 Oscillator Settling Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When a Crystal Oscillator is Used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time of at least 10 ms.
Table 5.3 Clock Frequency and Settling Time (Times are in ms)
STS2 STS1 STS0
0
0
0
1
1
0
1
1
*
*
Note: * Don’t care
Waiting Time
8,192 states
16,384 states
32,768 states
65,536 states
131,072 states
5 MHz
1.6
3.2
6.6
13.1
26.2
4 MHz
2.0
4.1
8.2
16.4
32.8
2 MHz
4.1
8.2
16.4
32.8
65.5
1 MHz
8.2
16.4
32.8
65.5
131.1
0.5 MHz
16.4
32.8
65.5
131.1
262.1
• When an External Clock is Used
Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.
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