HD6433832S Datasheet, PDF (299/560 Pages) Renesas Technology Corp – single-chip microcomputers

Simultaneous Transmit/Receive: Figure 10.21 shows a typical flow chart for transmitting and
receiving simultaneously. After SCI3 synchronization, follow the procedure below.
Start
1
Read bit TDRE in SSR
No
TDRE = 1?
Yes
2 Write transmit data in TDR
Read bit OER in SSR
Yes
OER = 1?
No
Read RDRF in SSR
No
RDRF = 1?
Yes
Read received data in RDR
1. Read the serial status register (SSR),
and after confirming that bit TDRE = 1,
write transmit data in the transmit data
register (TDR). When data is written to
TDR, TDRE is automatically cleared to 0.
2. Read the serial status register (SSR),
and after confirming that bit RDRF = 1,
read the received data from the receive
data register (RDR). When data is read
from RDR, RDRF is automatically cleared
to 0.
3. To continue transmitting and receiving
serial data, read bit RDRF and finish
reading RDR before the MSB (bit 7) of the
present frame is received. Also read bit
TDRE, check that it is set to 1, and write
the next data in TDR before the MSB of
the current frame has been transmitted.
When data is written to TDR, TDRE is
automatically cleared to 0; and when data
is read from RDR, RDRF is automatically
cleared to 0.
4. When an overrun error occurs, read bit
OER in SSR. After the necessary error
processing, be sure to clear OER to 0.
Data transmission and reception cannot
take place while bit OER is set to 1. See
figure 10.19 for overrun error processing.
4 Overrun error processing
Continue
Yes
3
transmitting and
receiving?
No
Clear bits TE and
RE in SCR3 to 0
End
Figure 10.21 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode
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