HD6433832S Datasheet, PDF (252/560 Pages) Renesas Technology Corp – single-chip microcomputers

End Address Register (EDAR)
Bit
7
6
—
—
Initial value
1
1
Read/Write
—
—
5
4
3
2
1
0
—
EDA4 EDA3 EDA2 EDA1 EDA0
1
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
EDAR is an 8-bit read/write register, for designating a transfer end address in the address space
(H'FF80 to H'FF9F) allocated to the 32-byte data buffer. The lower 5 bits of EDAR correspond to
the lower 5 bits of the address. The extent of continuous data transfer is defined in STAR and in
EDAR. If the same value is designated by STAR and EDAR, only 1 byte of data is transferred.
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
Upon reset, EDAR is initialized to H'E0.
Serial Control Register 2 (SCR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
GAP1 GAP0 CKS2 CKS1 CKS0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SCR2 is an 8-bit read/write register for selecting the serial clock, and for setting the gap inserted
between data during continuous transfer when SCI2 uses an internal clock.
Upon reset, SCR2 is initialized to H'E0.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bits 4 and 3—Gap Select 1, 0 (GAP1 to GAP0): When SCI2 uses an internal clock, gaps can be
inserted between successive data bytes. Bits 4 and 3 designate the length of these gaps. During a
gap, pin SCK₂ remains at the high level. When no gap is inserted, the STRB signal stays at the low
level.
Bit 4: GAP1
0
1
Bit 3: GAP0
0
1
0
1
Description
No gaps between bytes
(initial value)
A gap of 8 clock cycles is inserted between bytes
A gap of 24 clock cycles is inserted between bytes
A gap of 56 clock cycles is inserted between bytes
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