HD6433832S Datasheet, PDF (235/560 Pages) Renesas Technology Corp – single-chip microcomputers

TCG Clear Timing: TCG can be cleared at the rising edge, falling edge, or both edges of the
external input capture signal. Figure 9.14 shows the timing for clearing at both edges.
External input
capture signal
Internal input
capture signal F
Internal input
capture signal R
TCG
N
H'00
N
H'00
Figure 9.14 TCG Clear Timing
Timer G Operation States: Table 9.16 summarizes the timer G operation states.
Table 9.16 Timer G Operation States
Operation Mode Reset Active Sleep
Sub-
Watch active
Sub-
sleep
Standby
TCG
Input Reset Functions* Functions* Halted Functions/ Functions/ Halted
capture
Halted* Halted*
Interval Reset Functions* Functions* Retained Functions/ Functions/ Halted
Halted* Halted*
ICRGF
Reset Functions* Functions* Retained Functions/ Functions/ Retained
Halted* Halted*
ICRGR
Reset Functions* Functions* Retained Functions/ Functions/ Retained
Halted* Halted*
TMG
Reset Functions Retained Retained Functions Retained Retained
Note: * In active mode and sleep mode, if φ_W/2 is selected as the TCG internal clock, since the
system clock and internal clock are not synchronized with each other, a synchronization
circuit is used. This may result in a count cycle error of up to 1/φ (s). In subactive mode and
subsleep mode, if φ_W/2 is selected as the TCG internal clock, regardless of the subclock
φ/_SUB (φ_W/2, φ_W/4, φ_W/8) TCG and the noise canceller circuit run on an internal clock of φ_W/2. If
any other internal clock is chosen, TCG and the noise canceller circuit will not run, and the
input capture function will not operate.
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