HD6433832S Datasheet, PDF (259/560 Pages) Renesas Technology Corp – single-chip microcomputers

Data Transfer Operations
SCI2 Initialization: Data transfer on SCI2 first of all requires that SCI2 be initialized by software
as follows.
• With bit STF cleared to 0 in SCSR2, select pin functions and the transfer mode in registers
PMR2, PMR3, STAR, EDAR, and SCR2.
• The SCI2 pins double as general input/output ports. Switching between port and SCI2
functions is controlled in PMR3. CMOS output or NMOS open drain output can be selected in
PMR2. The serial clock and gaps between transferred bytes are set in SCR2.
• The start and end addresses of the transfer data area are set in STAR and EDAR. If the end
address is set smaller than the start address, as shown in figure 10.6, the transfer wraps around
from H'FF9F to H'FF80 and continues to the end address. If the start address and end address
are the same, only one byte of data will be transferred.
H'FF80
End
End address
Start
Start address
H'FF9F
Figure 10.6 Operation When End Address is Smaller than Start Address
Transmitting: A transmit operation is carried out as follows.
• Set bits SO2 and SCK2 in PMR3 TO 1 so that the respective pins function as SO₂ and SCK₂. If
necessary, set bit POF2 in port mode register 2 (PMR2) for NMOS open-drain output at pin
SO₂, and set bits CS and STRB in PMR3 to designate use of the CS and STRB pin functions.
• Select the serial clock and, in the case of internal clock operation, the data gap in SCR2.
• Write transmit data in the serial data buffer. This data will remain in the data buffer after
completion of the transfer. It is not necessary to rewrite the buffer when the same data is
retransmitted.
• Set the start address in the lower 5 bits of STAR, and the end address in the lower 5 bits of
EDAR.
• Set the start/busy flag (STF) to 1. If bit CS = 0 in PMR3, transmission starts as soon as STF is
set to 1. If CS = 1 in PMR3, transmission starts when CS goes low.
• After data transmission is complete, bit IRRS2 in interrupt request register 2 (IRR2) is
set to 1, and bit STF is cleared to 0.
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