HD6433832S Datasheet, PDF (354/560 Pages) Renesas Technology Corp – single-chip microcomputers

14.2.3 AC Characteristics
Table 14.3 lists the control signal timing, and tables 14.4 and 14.5 list the serial interface timing of
the H8/3832S, H8/3833S and H8/3834S.
Table 14.3 Control Signal Timing of H8/3832S, H8/3833S and H8/3834S
V_CC = 2.5 V to 5.5 V, AV_CC = 2.5 V to 5.5 V, V_SS = AV_SS = 0.0 V, T_a = –20°C to +75°C, including
subactive mode, unless otherwise specified.
Item
Applicable
Symbol Pins
Min Typ Max Unit Test Condition
Reference
Figure
System clock
f_OSC
oscillation frequency
OSC₁, OSC₂ 2.0 —
2.0 —
10.0 MHz V_CC = 4.0 V to 5.5 V
5.0
OSC clock (φ_OSC)
cycle time
t_OSC
OSC₁, OSC₂ 100.0 —
1000.0 ns V_CC = 4.0 V to 5.5 V 1
200.0 —
1000.0
Figure 14.1
System clock (φ)
t_cyc
2—
16
t_OSC
1
cycle time
——
2000.0 ns
Subclock oscillation f_W
frequency
X₁, X₂
— 32.768 — kHz
Watch clock (φ_w) cycle t_W
time
X₁, X₂
— 30.5 — µs
Subclock (φ_SUB) cycle t_subcyc
2—
8
t_W
2
time
Instruction cycle time
Oscillation stabilization t_rc
time (crystal oscillator)
2—
OSC₁, OSC₂ — —
——
——
—
t_cyc
t_subcyc
40.0 ms V_CC = 4.0 V to 5.5 V
60.0
V_CC = 2.7 V to 5.5 V
100.0
Oscillation stabilization t_rc
time
X₁, X₂
——
2
s
External clock high
t_CPH
width
OSC₁
40.0 —
80.0 —
— ns V_CC = 4.0 V to 5.5 V Figure 14.1
—
External clock low
t_CPL
OSC₁
width
40.0 —
80.0 —
— ns V_CC = 4.0 V to 5.5 V Figure 14.1
—
External clock rise time t_CPr
——
——
15.0 ns
20.0
V_CC = 4.0 V to 5.5 V Figure 14.1
External clock fall time t_CPf
——
——
15.0 ns
20.0
V_CC = 4.0 V to 5.5 V Figure 14.1
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
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