HD6433832S Datasheet, PDF (275/560 Pages) Renesas Technology Corp – single-chip microcomputers

Bit 3—Parity Error (PER): Bit 3 is a status flag indicating that a parity error has occurred during
asynchronous receiving.
Bit 3: PER
Description
0
Indicates that data receiving is in progress or has been completed*¹ (initial value)
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
1
Indicates that a parity error occurred in data receiving*²
Setting condition:
When the sum of 1s in received data plus the parity bit does not match the parity
mode bit (PM) setting in the serial mode register (SMR)
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and
keeps its previous state.
2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set.
While PER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
Bit 2—Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the
last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified
directly.
Bit 2: TEND
0
1
Description
Indicates that transmission is in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
Indicates that a transmission has ended
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
Bit 1—Multiprocessor Bit Receive (MPBR): Bit 1 holds the multiprocessor bit in data received
in asynchronous mode using a multiprocessor format. MPBR is a read-only bit and cannot be
modified.
Bit 1: MPBR
Description
0
Indicates reception of data in which the multiprocessor bit is 0* (initial value)
1
Indicates reception of data in which the multiprocessor bit is 1
Note: * If bit RE is cleared to 0 while a multiprocessor format is in use, MPBR retains its previous
state.
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